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[ 지원자격] ㆍ대학교 졸업(4년) 이상
ㆍ동일 직종 경력 3년 이상 |
[담당업무]
ㆍIP / SOC RTL Verification
ㆍIP level RTL Design
ㆍSOC RTL Integration Design
[필수사항]
ㆍIP or SOC RTL Design with Verilog-HDL(over 3 years)
ㆍIP or SOC RTL Verification(over 3 years)
ㆍCadence/Synopsys simulator tool experience
[우대사항]
ㆍSystemverilog based Design or Verification
ㆍUVM based Verification & Coverage for IP or SOC Level
ㆍUVM based Verification Environment Setup
ㆍSynopsys/Cadence UVM based VIP Verification Integration
ㆍMCU/CPU based Design/Verification
ㆍMagillem design integration tool
ㆍTop Design RTL integration
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ㆍDesign Synthesis/Formal/DFT/SDC
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