As a Verification Engineer on the Logic Design team, you will participate in the definition, implementation, and execution of our verification strategy, as well as being a key participant in the analysis of our IP/SoC verification quality of results. This position is a highly visible role, the simple purpose of which is to ensure the silicon works. By its design philosophy, RISC-V is highly configurable, and we have several different configurations in our design pipeline, with various combinations of supported instruction set and with various peripherals and bus interconnect architectures. Implementing design verification methodologies that can accommodate such variation is a challenging task, to be addressed in this role.

Principal Accountabilities

• Architect test methodologies applicable to a wide range of processor and IP/SoC designs
• Perform initial debug of test failures to identify design errors
• Collaborate closely with the design team to address any design errors
• Understand custom microprocessor and SoC designs from an architectural level, and use this understanding to envision effective verification strategies for these designs
• Create a test plan to codify this strategy, taking account of such issues as design feature priority, potential customer impact, coverage metrics generation and measurability, etc.
• Create test suites (UVM, C, or otherwise, as needed) to execute this strategy
• Drive the execution of these test suites (scripting, Makefiles, etc.)
• Analysis of test results, including RTL or higher-level debug of test failures
• Interact with the design team to help drive bug closure

Key Performance Measures

• Understanding SoC architecture and Bus architecture
• Skill for handling scripts, OOP high level languages, data structure, algorithms and so on
• Will and action to break down the repetitive or routine tasks

Qualifications

• A minimum of 3 years of recent experience with standard verification tools and methodologies (UVM, Verdi/DVE, Verilog, Makefiles, scripting languages, etc.). Especially in hands-on testbench and test suite generation
• A conscientious and thorough approach to Design Verification - Attention to detail. Thoroughness is essential in this role
• Solid understanding of processor, SoC architecture, Bus architecture (ex. AMBA, Tilelink), or a strong desire and ability to learn same
• A thorough understanding of the high-level verification flow methodology (testplan generation, test generation, failure analysis, code coverage, iteration until coverage closure)
• Ability to effectively assess the current state of a design’s verification posture, remaining state space to be covered, and efficient methods to achieve verification closure
• Knowledge of Verilog/System Verilog, digital simulation and debug with various verification tools (VCS, Xcelium, Questa, Verdi, etc)
• Ability to learn languages and methodologies that are not part of the industry standard approach to verification (Scala, Chisel, etc.)
• Ph.D or Master’s degree in Electrical Engineering, Computer architecture, or Computer Science is a plus
• Experience of Static Verification tools is a plus
• Ability to work with team playing based on opensource environment is a plus (ex. using Github)
• Experience with Perl, Python or similar scripting language is a plus