담당업무
ㆍFlatten or Hierarchical Physical Design Flow - Block Partitioning - Top & Sub Block Implementation - High Speed Block Hardening (CPU/GPU/NPU/DDR etc) - Timing/Congestion/Cross-Talk Noise Sign-Off ㆍLow Power Design Flow - UPF based P&R(Multi Voltage/Multi Supply) - Power Switch Cell / Level Shifter / ISO cell insertion - Wake-up Noise Analysis ㆍFlip Chip Flow - Bump Assignment & RDL Routing ㆍRC Extraction - Clock & Signal RC extraction ㆍPower & Signal Integrity - Dynamic/Static IR Drop Analysis & EM Analysis - Signal EM Analysis & Jitter Aware Clock & Data Path Handling ㆍPhysical Verification - DRC/LVS/ERC/ESD/DFM
스킬
ㆍPhysical Design 을 위한 EDA Tool 활용 능력
핵심역량
ㆍ
성실성,
적응성,
꼼꼼함
자격요건
ㆍ학력 : 학사 ㆍ경력 : ASIC/SOC Physical Design 2년 이상 경력 ㆍ전공 : 전기, 전자, 반도체 관련 공학 전공
우대사항
ㆍHierarchical Physical Design Top 레벨 처리 경험 ㆍPhysical Verification 업무 능력
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