대기업이 만든 NPU 전문기업 

Responsibilities

·           Develop test scenarios in test benches and create directed / constrained random tests, simulate and debug.

·           Regression triaging, along with analyzing coverage, improve flows and run RTL and gate level functional simulations.

·           Work closely with the design teams to review specifications and architecture, extract features, and define verification plan & coverage model.

Career Requirements

·           3+ years of related experience in verification(2+ years)

·           Analysis skills to debug RTL / gate design problems.

·           Knowledge and experience of System Verilog and System Verilog Assertion language.

·           Knowledge of simulation-based verification concepts such as scoreboard and functional coverage, etc.

·           Experience of UVM verification technology is desirable.

·           Automation skills using Perl, Python, Shell scripting, etc.

Preferred Requirements

·           5+ years of related experience in verification(3+ years)

·           Good working experience with C/C++.

·           Communication skills (written and verbal) to convey complex information to peers.

·           Detailed oriented and be able to plan and prioritize tasks effectively.

·           Self-motivated, able to work as a team player.